AMD Explains Power Efficient Design in Next Generation CPUs/GPUs - Carrizo APU to Double Efficiency of Kaveri APU

AMD's Futurity of Compute event was conducted recently  and had quite a lot of tidbits of interesting data. One such aspect was AMD's discussion of Ability Efficient blueprint in chip compages. AMD has previously made the claim on many occasions but this is the offset time they take gone into and so much item. One or two slides were recycled (with color changes) from their previous press releases simply most are new. The slide deck was provided to u.s. courtesy of DG Lee over at IYD.KR.

A slide from the outcome showing AMD' goal against the historical trend and the present tendency @AMD Public Domain

AMD won't rely on process shrinkage for power efficiency and achieving '25x by 2022'

Silicon processors haven't been on this earth for a very long time. Every bit the confusing engineering was in a archaic state when information technology get-go arrived, achieving huge amounts of power efficiency with each successive generation was easy to come by. However, in this decade we have entered the office of the bend where we are getting exponentially decreasing returns on every boosted unit of effort. Since a process shrink can put more than transistors in the same space and less electricity is required for the transistors to report their states, you get natural power efficiency jumps with every iteration, but optimizing compages with the same level of gains is another story altogether.

Another slide showing the workings of achieving a x to 20% power reduction @AMD Public Domain

However, as can be seen with the entire 28nm GPU fiasco, reliance on node shrinkage is a very unsafe matter. We have been stuck on 28nm for what, 3-4 years now? Which means that though you tin can cram more transistors by increasing the dice space, you won't become whatever more than efficient unless you optimize the architecture itself and it is with this context that the event held by AMD starts. They brainstorm of by showing some statistics: what the trend line for ability efficiency increase was earlier and what it is now (post 2000). And here is what AMD is promising; they volition beat not only the current trend line but the historical trend line as well by the 2022 marking ( in its mobile division atleast).

AMD talks about the low ability units of its Eco system (APUs) and how their inherent architecture enables them for huge power efficiency heave on the software level. They show some CPU-GPU power trading ratios on how workloads can be split between the CPU and GPU portion of an APU for much ameliorate heat dissipation and how the unified compages avoids back-up in memory/bus assuasive conservation of energy. Do keep in mind that 2022 is now pretty close, so AMD is challenge to be able to striking the 25x sweetness spot in approximately 5 years. AMD has also charted a graph similar to the compute one which shows how APUs tin can harness the growth of the GPU while keeping performance serial.

There are a couple of technical details as well explaining AMD's boost control system (not boosting software that doesn't benefit from higher clocks), efficient voltage command and power - battery tradeoffs among other things. The biggest way a scrap can conserve power is through the Idle state, and some of the slides mention how they tin can optimize the process so the CPU goes to sleep more hands and apace. Interestingly they also prove the predicted free energy efficiency of Carrizo APU which is approximately double that of the Kaveri APU. Non actually surprising but however interesting to know. All in all, the slides make a good read.

Source: https://wccftech.com/amd-talks-power-efficient-design-chips-carrizo-apu-double-efficiecy-kaveri-apu/

Posted by: renardsairch.blogspot.com

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